Non-volatile semiconductor devices, such as EEPROM devices, are both electrically erasable and programmable. Such devices retain data even after the power is terminated to the device. Non-volatile memory devices have a limited lifetime due to the endurance related stress such devices suffer each time they go through a program-erase cycle. The endurance of non-volatile memory devices is defined as the number of program/erase cycles that the memory device is capable of undergoing before device failure.
The main charge storage component of a non-volatile memory cell is a floating-gate electrode. Electrical charge is placed on the floating-gate electrode by transferring electrons from an underlying substrate to the floating-gate electrode through a tunnel oxide layer. The storage and removal of charge on the floating-gate electrode is the operative means by which data is stored in a non-volatile memory cell. The presence or absence of charge in the floating-gate electrode is determined by measuring the threshold voltage of a metal-oxide-semiconductor (MOS) transistor that is activated by the floating-gate electrode.
The threshold voltage of an MOS transistor is the minimum amount of voltage that must be applied to the gate electrode of the transistor before the transistor is turned "on." When the MOS transistor is turned on, electrical conduction takes place between the source and drain regions of the transistor. The presence or absence of charge on the floating-gate electrode is determined by measuring the amount of voltage necessary to turn the MOS transistor on. The threshold voltage of an MOS transistor having a floating-gate electrode will vary depending upon whether or not charge has been placed on the floating-gate electrode.
To cause electrons to transfer between the substrate and the floating-gate electrode, voltage potentials are applied to the substrate and to the source and drain regions, such that potential gradients are set up across an oxide layer underlying the floating-gate electrode. In one type of non-volatile memory device, the device is programmed by applying a high positive voltage to a control-gate electrode, and a low positive voltage to the drain region of the MOS transistor. These applied voltages transfer electrons from the substrate through the oxide layer and into the floating-gate electrode by hot carrier injection. Conversely, the device is erased by grounding the substrate, and applying a high positive voltage to either the source or drain region of the MOS transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and enter either the source or drain region in the semiconductor substrate.
In another type of non-volatile memory device used in programmable-logic-devices (PLDs), electron transfer is carried out by Fowler-Nordheim tunneling. A control-gate or program junction region (PJR) is formed in the substrate and is capacitively coupled to the floating-gate electrode. A voltage applied to the PJR is coupled to the floating-gate electrode, such that electrons tunnel through a tunnel oxide layer located between the PJR and the floating-gate electrode.
Over time, the data storage cells in the non-volatile memory device will be written and erased repeatedly as data is stored and removed from the various memory cells within the device. Since data storage relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide layer underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide layer can cause charge trapping sites to form within the tunnel oxide. The formation of these charge trapping sites is undesirable, because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode, a data error occurs in the memory cell. The charge loss from the floating-gate electrode caused by leakage through the tunnel oxide layer has not been a significant problem for devices having tunnel oxide thickness greater than about 100 angstroms. However, as non-volatile memory devices are scaled to smaller dimensions the thickness of the tunnel oxide layer is reduced to about 90 angstroms or less. At oxide thicknesses on the order of about 90 angstroms, the tunnel oxide layer more readily suffers program/erase cycling stress that results in premature device failure. Accordingly, screening for charge loss caused by tunnel oxide stress is of significant concern in non-volatile memory quality control procedures.